/freebsd/sys/amd64/include/ |
H A D | vmm_instruction_emul.h | f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems
|
H A D | vmm.h | f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems
|
/freebsd/sys/amd64/vmm/ |
H A D | vmm_instruction_emul.c | f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems
|
H A D | vmm.c | f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems
|
/freebsd/sys/amd64/vmm/intel/ |
H A D | vmx.c | f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems f7a9f178 Tue Jul 15 17:37:17 GMT 2014 Neel Natu <neel@FreeBSD.org> Add support for operand size and address size override prefixes in bhyve's instruction emulation [1].
Fix bug in emulation of opcode 0x8A where the destination is a legacy high byte register and the guest vcpu is in 32-bit mode. Prior to this change instead of modifying %ah, %bh, %ch or %dh the emulation would end up modifying %spl, %bpl, %sil or %dil instead.
Add support for moffsets by treating it as a 2, 4 or 8 byte immediate value during instruction decoding.
Fix bug in verify_gla() where the linear address computed after decoding the instruction was not being truncated to the effective address size [2].
Tested by: Leon Dang [1] Reported by: Peter Grehan [2] Sponsored by: Nahanni Systems
|